Suppression of offset, offset drift, and 1/f noise during analog/digital conversion is needed, in particular, to digitally regulate and control gradient amplifiers in magnetic resonance imaging.
A gradient amplifier having a basic field of greater than 1 Tesla (T) and a gradient strength of greater than 30 mT/m empirically requires a current stability of less than 0.25 ppm in the frequency range of 0.1 Hz to 10 Hz, which corresponds to a ratio of 1:4,000,000. The current of gradient amplifiers for magnetic resonance tomography is therefore nowadays regulated in an analog manner and has corresponding low-noise components in its signal path.
If the current of the gradient amplifier is intended to be regulated in a digital manner, an analog/digital converter (ADC) is used. FIG. 1 depicts a block diagram of a gradient amplifier 1 for magnetic resonance tomography. The gradient amplifier 1 regulates a current in the gradient coil 3 connected to the gradient amplifier 1 according to a digital desired value 2 generated by a controller of a magnetic resonance installation.
The current is recorded by a current measuring unit 4, (for example, a very accurate DC current transformer), which feeds its secondary current to a measuring resistor 8 (e.g., shunt) that is part of the current actual value preprocessor 7. The measurement voltage 9 at the measuring resistor 8 is now a measure of the measured gradient current. The measurement voltage 9, which needs to be amplified under certain circumstances, in the measuring resistor 8, that is to say the analog current actual value, is processed by the analog actual value preprocessor 10. The measurement voltage 9 is converted, by an analog/digital converter (ADC) 11, into a digital current actual value 13 that is now present in the ADC control unit 12. The ADC control unit 12 controls the times at which the ADC 11 is intended to carry out conversion and appropriately receives the converted values from the ADC 11.
In order to regulate the gradient current, the digital current actual value 13 is compared with the desired value 2 in the regulating and drive unit 14. The regulating and drive unit 14 generates the drive signal 15 for the output stage 6 of the gradient amplifier 1, to which the gradient coil 3 is connected. The current actual value preprocessor 7 and the regulating and drive unit 14 are part of a regulating and control unit 5.
FIG. 2 depicts a block diagram of the further processing of the analog current actual value 9 in the analog actual value preprocessor 10 and the ADC 11. The analog current actual value 9 may be passed via an anti-aliasing filter 16, for example, via a low-pass filter.
Upstream of the ADC 11, a slight signal ripple (e.g., dithering, dither signal) is added by the dithering unit 17 to the current actual value filtered in this manner in order to obliterate the quantization limits of the ADC 11 for low frequencies. The voltage of the dithering unit 17 may be, for example, a triangular voltage, the peak-to-peak value of which corresponds at least to a “Least Significant Bit” (LSB) at the input of the ADC 11 and the frequency of which differs from the sampling frequency (e.g., conversion frequency) of the ADC 11.
In the block diagram A) in FIG. 2, the signal provided with dithering by the dithering unit 17 is additionally passed via an inverter 18 and is then supplied to the ADC 11 with differential inputs. It is likewise possible to supply the dithering to only one input of the ADC 11 by adding the dithering to the signal downstream of the inverter 18, for example. As a result, the ADC 11 is no longer driven in an exactly symmetrical manner; however, since the dithering has only a level of one LSB or a few LSBs, this may be tolerated.
The block diagram B) in FIG. 2 illustrates how the ADC 11 may also be driven using a so-called “single-ended” signal, in which case the inverter 18 according to block diagram A) is not required. In this case, the dithering from the dithering unit 17 is simply fed into the reference input and thus need not be added to the filtered signal.
The conversion by the ADC 11 is triggered by an ADC control unit 12 using the control signal “Convert”. Before the control signal “Convert” is applied, the ADC 11 is receptive to the signal (e.g., “sample”) applied to its inputs and holds this signal internally using the control signal “Convert” (e.g., “hold”). At the end of the conversion process, the new data with the bit width “n” are present at the output “Data_out” of the ADC 11 and the ADC 11 uses the output “ready” to signal the acceptance of the n bits of data from the output “Data_out” to the ADC control unit 12. At the end of the conversion process, the ADC 11 changes to the “sample” state again and connects its internal memory (e.g., a capacitor) to the inputs +IN and −IN again.
Circuit arrangements according to FIG. 2 are known. For example, the published patent application EP 1 134 898 A2 describes an ADC circuit arrangement with dithering.
The disadvantage of circuit arrangements according to FIG. 2 is that the stability required for magnetic resonance high-field systems (e.g., ≧1 Tesla) may not be achieved at low frequencies using the available ADC 11. A stability of less than 0.25 ppm is achieved in the frequency range of 0.1 Hz to 10 Hz, which corresponds to a stable resolution and accuracy of at least 22 bits. In this case, it is assumed that other components, (e.g., the current transformer 4), are ideal and do not contribute to the overall noise.